View AD5410ACPZ_4686154.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Preliminary Technical Data
FEATURES
12/16-Bit Resolution and Monotonicity Current Output Ranges: 4-20mA, 0-20mA or 0-24mA 0.1% typ Total Unadjusted Error (TUE) 5ppm/C Output Drift Flexible Serial Digital Interface On-Chip Output Fault Detection On-Chip Reference (10 ppm/C Max) Asynchronous CLEAR Function Power Supply (AVDD) Range 10.8V to 60 V; AD5410/AD5420ACPZ 10.8V to 40V; AD5410/AD5420AREZ Output Loop Compliance to AVDD - 2.5 V Temperature Range: -40C to +85C TSSOP and LFCSP Packages
Single Channel, 16-Bit, Serial Input, Current Source DAC AD5410/AD5420
GENERAL DESCRIPTION
The AD5410/AD5420 is a low-cost, precision, fully integrated 12/16-bit converter offering a programmable current source output designed to meet the requirements of industrial process control applications.The output current range is programmable to 4mA to 20 mA, 0mA to 20mA or an over range function of 0mA to 24mA. The output is open circuit protected and can drive inductive loads of 1H. The device is specified to operate with a power supply range from 10.8 V to 40V AD5410/AD5420AREZ) or 10.8V to 60V (AD5410/AD5420ACPZ). Output loop compliance is 0 V to AVDD - 2.5 V. The flexible serial interface is SPI and MICROWIRE compatible and can be operated in 3-wire mode to minimize the digital isolation required in isolated applications. The device also includes a power-on-reset function ensuring that the device powers up in a known state and an asynchronous CLEAR pin which sets the output to the low end of the selected current range. The total output error is typically 0.1% FSR. Table 1. Related Devices
Part Number AD5422 Description Single Channel, 16-Bit, Serial Input Current Source and Voltage Output DAC Single Channel, 12-Bit, Serial Input Current Source and Voltage Output DAC Single Channel, 12-Bit, Serial Input Current Source DAC
APPLICATIONS
Process Control Actuator Control PLC
AD5412
AD5410
Rev. PrE
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved.
AD5410/AD5420 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Functional Block Diagram .............................................................. 3 Specifications..................................................................................... 4 AC Performance Characteristics ................................................ 6 Timing Characteristics ................................................................ 7 Absolute Maximum Ratings............................................................ 9 ESD Caution.................................................................................. 9 Pin Configuration and Function Descriptions........................... 10 Typical Performance Characteristics ........................................... 11 Terminology .................................................................................... 16 Theory of Operation ...................................................................... 17 Architecture................................................................................. 17 Serial Interface ............................................................................ 17 power-up state............................................................................. 21 Transfer Function ....................................................................... 21 Data Register ............................................................................... 21 Control Register.......................................................................... 21
Preliminary Technical Data
RESET register ............................................................................ 22 Status register .............................................................................. 22 Features ............................................................................................ 23 fault alert...................................................................................... 23 Asynchronous Clear (CLEAR) ................................................. 23 Internal Reference ...................................................................... 23 External current setting resistor............................................... 23 Digital Power Supply.................................................................. 23 External boost function............................................................. 23 digital Slew rate control ............................................................. 24 IOUT Filtering Capacitors (LFCSP PAckage) ............................ 25 Applications Information .............................................................. 26 driving inductive loads .............................................................. 26 Transient voltage protection ..................................................... 26 Layout Guidelines....................................................................... 26 Galvanically Isolated Interface ................................................. 26 Microprocessor Interfacing....................................................... 26 Thermal and supply considerations......................................... 27 Outline Dimensions ....................................................................... 28 Ordering Guide .......................................................................... 28
REVISION HISTORY
PrE - Preliminary Version. May 2, 2008
Rev. PrE | Page 2 of 30
Preliminary Technical Data FUNCTIONAL BLOCK DIAGRAM
DVCC SELECT DVCC CAP1* CAP2*
AD5410/AD5420
AVDD
CLEA R SELECT CLEA R LATCH SCLK SDIN SDO
AD5410/AD5420
R2 R3 BOOST INPUT SHIFT REGISTER AND CONTROL LOGIC
16
/
12/16-Bit DAC
IOUT FAULT RSET
R1 POWER ON RESET VREF
DGND*
REFOUT
REFIN
AGND
*LFCSP Package
Figure 1.
Rev. PrE | Page 3 of 30
AD5410/AD5420 SPECIFICATIONS
Preliminary Technical Data
AVDD = 10.8V to 40V/60V1, AGND = DGND = 0 V, REFIN= +5 V external; DVCC = 2.7 V to 5.5 V, RL = 300, HL = 50mH; all specifications TMIN to TMAX, 0 to 24 mA range unless otherwise noted. Table 2.
Parameter Output Current Ranges Value2 0 to 24 0 to 20 4 to 20 12 16 0.3 5 0.024 0.012 1 0.05 5 0.05 8 0.05 8 AVDD - 2.5 TBD TBD 1200 1 1 50 Unit mA mA mA Bits Bits % FSR max ppm/C typ % FSR max % FSR max LSB max % FSR max ppm FSR/C typ % FSR max ppm FSR/C max % FSR max ppm FSR/C V max ppm FSR/500 hr typ ppm FSR/1000 hr typ max H max A/V max M typ Test Conditions/Comments
ACCURACY Resolution Total Unadjusted Error (TUE) TUE TC3 Relative Accuracy (INL) Differential Nonlinearity (DNL) Offset Error Offset Error Drift Gain Error Gain TC3 Full-Scale Error Full-Scale TC3 OUTPUT CHARACTERISTICS3 Current Loop Compliance Voltage Output Current Drift vs. Time Resistive Load Inductive Load DC PSRR Output Impedance REFERENCE INPUT/OUTPUT Reference Input3 Reference Input Voltage DC Input Impedance Reference Range Reference Output Output Voltage Reference TC Output Noise (0.1 Hz to 10 Hz)3 Noise Spectral Density3 Output Voltage Drift vs. Time3 Capacitive Load Load Current Short Circuit Current Line Regulation3 Load Regulation3 Thermal Hysteresis3 DIGITAL INPUTS3 VIH, Input High Voltage VIL, Input Low Voltage
AD5410 AD5420 Over temperature, supplies, and time, typically 0.1% FSR AD5410 AD5420 Guaranteed monotonic
@ 25C, error at other temperatures obtained using gain TC @ 25C, error at other temperatures obtained using gain TC
5 30 4 to 5 4.998 to 5.002 10 18 120 40 50 TBD 5 7 10 TBD TBD 2 0.8
V nom k min V min to V max V min to V max ppm/C max V p-p typ nV/Hz typ ppm/500 hr typ ppm/1000 hr typ nF max mA typ mA typ ppm/V typ ppm/mA ppm V min V max
Rev. PrE | Page 4 of 30
1% for specified performance Typically 40 k
@ 25C
@ 10 kHz
DVCC = 2.7 V to 5.5 V, JEDEC compliant
Preliminary Technical Data
Parameter Input Current Pin Capacitance DIGITAL OUTPUTS 3 SDO VOL, Output Low Voltage VOH, Output High Voltage High Impedance Leakage Current High Impedance Output Capacitance FAULT VOL, Output Low Voltage VOL, Output Low Voltage VOH, Output High Voltage POWER REQUIREMENTS AVDD DVCC Input Voltage Output Voltage Output Load Current Short Circuit Current AIDD DICC Power Dissipation Value2 1 10 Unit A max pF typ Test Conditions/Comments Per pin Per pin
AD5410/AD5420
0.4 DVCC - 0.5 1
V max V min A max
sinking 200 A sourcing 200 A
5 0.4 0.6 3.6 10.8 to 60 10.8 to 40 2.7 to 5.5 4.5 5 20 TBD 1 TBD TBD TBD
pF typ V max V typ V min V min to V max V min to V max V min to V max V typ mA typ mA typ mA mA max mW typ mW typ mW typ 10k pull-up resistor to DVCC @ 2.5 mA 10k pull-up resistor to DVCC AD5410/AD5420ACPZ AD5410/AD5420AREZ Internal supply disabled DVCC can be overdriven up to 5.5V
VIH = DVCC, VIL = GND, TBD mA typ AVDD = 40V AVDD = 60V AVDD = 15V
1 2
Maximum supply for the AD5410/AD5420BREZ is 40V, Maximum supply for the AD5410/AD5420BCPZ is 60V Temperature range: -40C to +85C; typical at +25C. 3 Guaranteed by design and characterization, not production tested.
Rev. PrE | Page 5 of 30
AD5410/AD5420
AC PERFORMANCE CHARACTERISTICS
Preliminary Technical Data
AVDD = 10.8V to 40V/60V1, AGND = DGND = 0 V, REFIN= +5 V external; DVCC = 2.7 V to 5.5 V, RL = 300, HL = 50mH; all specifications TMIN to TMAX, 0 to 24 mA range unless otherwise noted. Table 3.
Parameter2 DYNAMIC PERFORMANCE Output Current Settling Time AC PSRR
1 2
Unit TBD TBD TBD s typ s typ dB
Test Conditions/Comments To 0.1% FSR , L = 1H To 0.1% FSR , L < 1mH 200mV 50/60 Hz sinewave superimposed on power supply voltage
Maximum supply for the AD5410/AD5420BREZ is 40V, Maximum supply for the AD5410/AD5420BCPZ is 60V Guaranteed by design and characterization, not production tested.
Rev. PrE | Page 6 of 30
Preliminary Technical Data
TIMING CHARACTERISTICS
AD5410/AD5420
AVDD = 10.8V to 40V/60V1, AGND = DGND = 0 V, REFIN= +5 V external; DVCC = 2.7 V to 5.5 V, RL = 300, HL = 50mH; all specifications TMIN to TMAX, 0 to 24 mA range unless otherwise noted. Table 4.
Parameter2, 3, 4 Write Mode t1 t2 t3 t4 t5 t5 t6 t7 t8 t9 t10 Readback Mode t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 Daisychain Mode t21 t22 t23 t24 t25 t26 t27 t28 t29 Limit at TMIN, TMAX 33 13 13 13 40 5 5 5 40 20 5 82 33 33 13 40 5 5 40 40 33 82 33 33 13 40 5 5 40 40 Unit ns min ns min ns min ns min ns min s min ns min ns min ns min ns min s max ns min ns min ns min ns min ns min ns min ns min ns min ns max ns max ns min ns min ns min ns min ns min ns min ns min ns min ns max Description SCLK cycle time SCLK low time SCLK high time LATCH delay time LATCH high time LATCH high time (After a write to the CONTROL register) Data setup time Data hold time LATCH low time CLEAR pulsewidth CLEAR activation time SCLK cycle time SCLK low time SCLK high time LATCH delay time LATCH high time Data setup time Data hold time LATCH low time Serial output delay time (CL SDO5 = 15pF) LATCH rising edge to SDO tri-state SCLK cycle time SCLK low time SCLK high time LATCH delay time LATCH high time Data setup time Data hold time LATCH low time Serial output delay time (CL SDO5 = 15pF)
1 2
Maximum supply for the AD5410/AD5420AREZ is 40V, Maximum supply for the AD5410/AD5420ACPZ is 60V Guaranteed by characterization. Not production tested. 3 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. 4 See Figure 2, Figure 3, and Figure 4. 5 CL SDO = Capacitive load on SDO output. Rev. PrE | Page 7 of 30
AD5410/AD5420
t1
SCLK 1 2 24
Preliminary Technical Data
t2
t3
t4
t5
LATCH
t6
SDIN DB23
t7
t8
DB0
CLEAR
t9
t10
OUTPUT
Figure 2. Write Mode Timing Diagram
t11
SCLK 1 2 24 1 2 8 9 22 23 24
t12
t13
t14
t15
LATCH
t16
SDIN DB23
t17
t18
DB0 DB23 NOP CONDITION DB0
INPUT WORD SPECIFIES REGISTER TO BE READ SDO UNDEFINED DATA X X X
t 19
X DB15 SELECTED REGISTER DATA CLOCKED OUT DB0
t 20
FIRST 8 BITS ARE DON'T CARE BITS
Figure 3. Readback Mode Timing Diagram
t21
SCLK 1 2 24 25 26 48
t22
t23
t24
t25
LATCH
t26
SDIN DB23 INPUT WORD FOR DAC N SDO DB23 UNDEFINED DB0 DB23
t27
t28
DB0
t 29
DB0 DB23
INPUT WORD FOR DAC N-1 DB0 INPUT WORD FOR DAC N
Figure 4. Daisychain Mode Timing Diagram
Rev. PrE | Page 8 of 30
Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS
TA = 25C unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. Table 5.
Parameter AVDD to AGND, DGND DVCC to AGND, DGND Digital Inputs to AGND, DGND Digital Outputs to AGND, DGND REFIN/REFOUT to AGND, DGND IOUT to AGND, DGND AGND to DGND Operating Temperature Range Industrial Storage Temperature Range Junction Temperature (TJ max) 24-Lead TSSOP Package JA Thermal Impedance 40-Lead LFCSP Package JA Thermal Impedance Power Dissipation Lead Temperature Soldering Rating -0.3V to 60V -0.3 V to +7 V -0.3 V to DVCC + 0.3 V or 7 V (whichever is less) -0.3 V to DVCC + 0.3 V or 7V (whichever is less) -0.3 V to +7 V -0.3V to AVDD -0.3V to +0.3V -40C to +851C -65C to +150C 125C 42C/W 28C/W (TJ max - TA)/ JA JEDEC Industry Standard J-STD-020
1
AD5410/AD5420
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Power dissipated on chip must be de-rated to keep junction temperature below 125C. Assumption is max power dissipation condition is sourcing 24mA into Ground from AVDD with a 3mA on-chip current.
Rev. PrE | Page 9 of 30
Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DVCC AVDD GND NC NC NC NC NC
AD5410/AD5420
GND DVCC FAULT GND GND CLEAR
1 2 3 4 5 6
24 23
AVDD NC NC NC
NC 1 FAULT 2 GND 3 GND 4 CLEAR 5 LATCH 6 SCLK 7 SDIN 8 SDO 9 NC 10
40
39
38
37
36
35
34
NC
33
32
31 30 NC 29 CAP2 28 CAP1 27 BOOST
AD5420
22 21
20 BOOST TOP VIEW (Not to Scale) 19 I OUT 18 17 16 15 14 13
NC
26 IOUT 25 NC 24 NC 23 DVCC SELECT 22 NC 21 NC 20
AD5420
TOP VIEW (Not to Scale)
LATCH 7 SCLK SDIN
8 9
NC NC DVCC SELECT REFIN REFOUT RSET
SDO 10 AGND 11 GND 12
11
12
13
14
15
16
17
18
19
RSET
REFOUT
REFIN
DGND
GND
GND
NC
NC
Figure 5. TSSOP Pin Configuration
Figure 6. LFCSP Pin Configuration
Table 6. Pin Function Descriptions
TSSOP Pin No. 1,4,5,12 2 3 LFCSP Pin No. 3,4,15,14,37 39 2 Mnemonic GND DVCC FAULT Description These pins must be connected to 0V. Digital Supply Pin. Voltage ranges from 2.7 V to 5.5 V. Fault alert, This pin is asserted low when an open circuit is detected in current mode or an over temperature is detected. Open drain output, must be connected to a pull-up resistor. No Connection.
17,18,21,22, 23
6 7 8 9 10 11 N/A 13 14 15 16
1,10,11,19, 20,21,22,24,25, 30,31,32,33,34, 35,38,40 5 6 7 8 9 12 13 16 17 18 23
NC
CLEAR LATCH SCLK SDIN SDO AGND DGND RSET REFOUT REFIN DVCC SELECT IOUT BOOST CAP1 CAP2 AVDD AGND
19 20 N/A N/A 24 Paddle
26 27 28 29 36 Paddle
Active High Input. Asserting this pin will set the current output to the bottom of the selected range. Positive edge sensitive latch, a rising edge will parallel load the input shift register data into the DAC register, also updating the output. Serial Clock Input. Data is clocked into the shift register on the rising edge of SCLK. This operates at clock speeds up to 30 MHz. Serial Data Input. Data must be valid on the rising edge of SCLK. Serial Data Output. Used to clock data from the serial register in daisy-chain or readback mode. Data is clocked out on the falling edge of SCLK. See Figure 3 and Figure 4. Ground reference pin for analog circuitry. Ground reference pin for digital circuitry. (AGND and DGND are internally connected in TSSOP package). An external, precision, low drift 15k current setting resistor can be connected to this pin to improve the IOUT temperature drift performance. Refer to Features section. Internal Reference Voltage Output. REFOUT = 5 V 2 mV. External Reference Voltage Input. Reference input range is 4 V to 5 V. REFIN = 5 V for specified performance. This pin when connected to GND disables the internal supply and an external supply must be connected to the DVCC pin. Leave this pin unconnected to enable the internal supply. Refer to features section. Current output pin. Optional external transistor connection. Connecting an external transistor will reduce the power dissipated in the AD5410/AD5420. Refer to the features section. Connection for optional output filtering capacitor. Refer to Features section. Connection for optional output filtering capacitor. Refer to Features section. Positive Analog Supply Pin. Voltage ranges from 10.8V to 40V/60V. Ground reference for analog circuitry.
Rev. PrE | Page 10 of 30
AGND
NC
Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS
AD5410/AD5420
Figure 7. Integral Non Linearity vs. Code
Figure 10. Integral Non Linearity vs. Temperature
Figure 8.Differential Non Linearity vs. Code
Figure 11. Differential Non Linearity vs. Temperature
Figure 9. Total Unadjusted Error vs. Code
Figure 12. Integral Non Linearity vs. Supply
Rev. PrE | Page 11 of 30
AD5410/AD5420
Preliminary Technical Data
Figure 13. Differential Non Linearity vs. Supply Voltage
Figure 16. Total Unadjusted Error vs. Reference Voltage
Figure 14. Integral Non Linearity vs. Reference Voltage
Figure 17. Total Unadjusted Error vs. Supply Voltage
Figure 15. Differential Non Linearity vs. Reference Voltage
Figure 18. Offset Error vs. Temperature
Rev. PrE | Page 12 of 30
Preliminary Technical Data
AD5410/AD5420
Figure 19. Gain Error vs. Temperature
Figure 21. IOUT vs. Time on Power-up
Figure 20. Voltage Compliance vs. Temperature
Figure 22. IOUT vs. Time on Output Enabled
Figure 23. DICC vs.Logic Input Voltage
Figure 24. AIDD vs AVDD
Rev. PrE | Page 13 of 30
AD5410/AD5420
Preliminary Technical Data
Figure 25. DVCC Output Voltage vs. DICC Load Current
Figure 28. Refout Output Noise (100kHz Bandwidth)
Figure 26. Refout Turn-on Transient
Figure 29. Refout Line Transient
Figure 27. Refout Output Noise (0.1Hz to 10Hz Bandwidth)
Figure 30. Refout Load Transient
Rev. PrE | Page 14 of 30
Preliminary Technical Data
AD5410/AD5420
Figure 31. Refout Histogram of Thermal Hysteresis
Figure 32. Refout Voltage vs. Load Current
Rev. PrE | Page 15 of 30
AD5410/AD5420 TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy, or integral nonlinearity (INL), is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot can be seen in Figure 7 Differential Nonlinearity (DNL) Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot can be seen in Figure 8. Monotonicity A DAC is monotonic if the output either increases or remains constant for increasing digital input code. The AD5724R/ AD5734R/AD5754R are monotonic over their full operating temperature range. Full-Scale Error Full-Scale error is a measure of the output error when full-scale code is loaded to the DAC register. Ideally, the output should be full-scale - 1 LSB. Full-scale error is expressed in percent of full-scale range (% FSR). Zero-Scale TC This is a measure of the change in zero-scale error with a change in temperature. Zero-scale error TC is expressed in ppm FSR/C. Gain Error This is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from ideal expressed in % FSR. A plot of gain error vs. temperature can be seen in Table TBD Gain TC This is a measure of the change in gain error with changes in temperature. Gain Error TC is expressed in ppm FSR/C.
Preliminary Technical Data
Total Unadjusted Error Total unadjusted error (TUE) is a measure of the output error taking all the various errors into account, namely INL error, offset error, gain error, and output drift over supplies, temperature, and time. TUE is expressed in % FSR. Current Loop Voltage Compliance The maximum voltage at the IOUT pin for which the output currnet will be equal to the programmed value. Power Supply Rejection Ratio (PSRR) PSRR indicates how the output of the DAC is affected by changes in the power supply voltage. Reference TC Reference TC is a measure of the change in the reference output voltage with a change in temperature. It is expressed in ppm/C. Line Regulation Line regulation is the change in reference output voltage due to a specified change in supply voltage. It is expressed in ppm/V. Load Regulation Load regulation is the change in reference output voltage due to a specified change in load current. It is expressed in ppm/mA. Thermal Hysteresis Thermal hysteresis is the change of reference output voltage after the device is cycled through temperatures from +25C to -40C to +85C and back to +25C. This is a typical value from a sample of parts put through such a cycle. See Table TBDfor a histogram of thermal hysteresis.
VO _ HYS = VO (25 C) - VO _ TC
VO _ HYS ( ppm) = VO (25 C) - VO _ TC VO (25 C) x 10 6
where:
VO(25C) = VO at 25C VO_TC = VO at 25C after temperature cycle
Rev. PrE | Page 16 of 30
AD5410/AD5420 THEORY OF OPERATION
The AD5410/AD5420 is a precision digital to current loop output converter designed to meet the requirements of industrial process control applications. It provides a high precision, fully integrated, low cost single-chip solution for generating current loop outputs. The current ranges available are; 0 to 20mA, 0 to 24mA and 4 to 20mA, The desired output configuration is user selectable via the CONTROL register.
Preliminary Technical Data
Reference Buffers
The AD5410/AD5420 can operate with either an external or internal reference. The reference input has an input range of 4 V to 5 V, 5 V for specified performance. This input voltage is then buffered before it is applied to the DAC.
SERIAL INTERFACE
The AD5410/AD5420 is controlled over a versatile 3-wire serial interface that operates at clock rates up to 30 MHz. It is compatible with SPI(R), QSPITM, MICROWIRETM, and DSP standards.
ARCHITECTURE
The DAC core architecture of the AD5410/AD5420 consists of two matched DAC sections. A simplified circuit diagram is shown in Figure 33. The 4 MSBs of the 12/16-bit data word are decoded to drive 15 switches, E1 to E15. Each of these switches connects 1 of 15 matched resistors to either ground or the reference buffer output. The remaining 8/12 bits of the dataword drive switches S0 to S11 of a 8/12-bit voltage mode R-2R ladder network.
VOUT 2R 2R S0 VREF 2R S1 2R S7/S11 2R E1 2R E2 2R E15
Input Shift Register
The input shift register is 24 bits wide. Data is loaded into the device MSB first as a 24-bit word under the control of a serial clock input, SCLK. Data is clocked in on the rising edge of SCLK. The input register consists of 8 control bits and 16 data bits as shown in
8/12-BIT R-2R LADDER
FOUR MSBs DECODED INTO 15 EQUAL SEGMENTS
Figure 33. DAC Ladder Structure
The voltage output from the DAC core is converted to a current (see diagram, Figure 34) which is then mirrored to the supply rail so that the application simply sees a current source output with respect to ground.
AVDD R2 T2 12/16-BIT DAC T1 A1 A2 IOUT R3
R1
Figure 34. Voltage to Current conversion circuitry
Rev. PrE | Page 17 of 30
AD5410/AD5420
Table 7. The 24 bit word is unconditionally latched on the rising edge of LATCH. Data will continue to be clocked in irrespective of the state of LATCH, on the rising edge of LATCH the data that is present in the input register will be latched, in other words the last 24 bits to be clocked in before the rising edge of
Preliminary Technical Data
LATCH will be the data that is latched. The timing diagram for this operation is shown in Figure 2.
Rev. PrE | Page 18 of 30
Preliminary Technical Data
Table 7. Input Shift Register Format
MSB D23 D22 D21 D20 D19 D18 ADDRESS WORD D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 DATA WORD D6
AD5410/AD5420
LSB D0
D5
D4
D3
D2
D1
Table 8. Address Word Functions
Address Word 00000000 00000001 00000010 01010101 01010110 Function No Operation (NOP) DATA Register Readback register value as per Read Address (See Table 10) CONTROL Register RESET Register
CONTROLLER DATA OUT SERIAL CLOCK CONTROL OUT
AD5410/ AD5420*
SDIN SCLK LATCH
DATA IN
SDO
SDIN
Standalone Operation
The serial interface works with both a continuous and noncontinuous serial clock. A continuous SCLK source can only be used if LATCH is taken high after the correct number of data bits have been clocked in. In gated clock mode, a burst clock containing the exact number of clock cycles must be used, and LATCH must be taken high after the final clock to latch the data. The first rising edge of SCLK that clocks in the MSB of the dataword marks the beginning ot the write cycle. Exactly 24 rising clock edges must be applied to SCLK before LATCH is brought high. If LATCH is brought high before the 24th rising SCLK edge, the data written will be invalid. If more than 24 rising SCLK edges are applied before LATCH is brought high, the input data will also be invalid.
AD5410/ AD5420*
SCLK LATCH
SDO
SDIN
AD5410/ AD5420*
SCLK LATCH
SDO
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 35. Daisy Chaining the AD5410/AD5420
Rev. PrE | Page 19 of 30
AD5410/AD5420
Daisy-Chain Operation
For systems that contain several devices, the SDO pin can be used to daisy chain several devices together as shown in Figure 35. This daisy-chain mode can be useful in system diagnostics and in reducing the number of serial interface lines. Daisychain mode is enabled by setting the DCEN bit of the CONTROL register. The first rising edge of SCLK that clocks in the MSB of the dataword marks the beginning of the write cycle. SCLK is continuously applied to the input shift register. If more than 24 clock pulses are applied, the data ripples out of the shift register and appears on the SDO line. This data is valid on the rising edge of SCLK having been clocked out on the previous falling SCLK edge. By connecting the SDO of the first device to the SDIN input of the next device in the chain, a multidevice interface is constructed. Each device in the system requires 24 clock pulses. Therefore, the total number of clock cycles must equal 24 x N, where N is the total number of AD5410/AD5420 devices in the chain. When the serial transfer to all devices is complete, LATCH is taken high. This latches the input data in each device in the daisy chain. The serial clock can be a continuous or a gated clock. A continuous SCLK source can only be used if LATCH is taken high after the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles
Preliminary Technical Data
must be used, and LATCH must be taken high after the final clock to latch the data. See Figure 4 for a timing diagram.
Readback Operation
Readback mode is invoked by setting the address word and read address as shown in Table 9 and Table 10 when writing to the input register. The next write to the AD5410/AD5420 should be a NOP command which will clock out the data from the previously addressed register as shown in Figure 3. By default the SDO pin is disabled, after having addressed the AD5410/AD5420 for a read operation, a rising edge on LATCH will enable the SDO pin in anticipation of data being clocked out, after the data has been clocked out on SDO, a rising edge on LATCH will disable (tri-state) the SDO pin once again. To read back the data register for example, the following sequence should be implemented: 1. Write 0x020001 to the AD5410/AD5420 input register. This configures the part for read mode with the data register selected. Follow this with a second write, a NOP condition, 0x000000 During this write, the data from the register is clocked out on the SDO line.
2.
Table 9. Input Shift Register Contents for a read operation
MSB D23 0 D22 0 D21 0 D20 0 D19 0 D18 0 D17 1 D16 0 D15 X D14 X D13 X D12 X D11 X D10 X D9 X D8 X D7 X D6 X D5 X D4 X D3 X D2 X LSB D1 D0 Read Address
Table 10. Read Address Decoding
Read Address 00 01 10 Function Read Status Register Read Data Register Read Control Register
Rev. PrE | Page 20 of 30
Preliminary Technical Data
POWER-UP STATE
On power-up of the AD5410/AD5420, the power-on-reset circuit ensures that all registers are loaded with zero-code, as such the output will be disabled (tri-state).
AD5410/AD5420
20mA I OUT = N x D 2
TRANSFER FUNCTION
For the 0 to 20mA, 0 to 24mA and 4 to 20mA current output ranges the output current is respectively expressed as;
24mA I OUT = N x D 2 16mA I OUT = N x D + 4mA 2
where:
D is the decimal equivalent of the code loaded to the DAC. N is the bit resolution of the DAC.
DATA REGISTER
The DATA register is addressed by setting the control word of the input shift register to 0x01. The data to be written to the DATA register is entered in positions D15 to D4 for the AD5410 and D15 to D0 for the AD5420 as shown in Table 11 and Table 12.
Table 11. Programming the AD5410 Data Register
MSB D15 D14 D13 D12 D11 D10 D9 12-BIT DATA WORD D8 D7 D6 D5 D4 D3 X D2 X D1 X LSB D0 X
Table 12. Programming the AD5420 Data Register
MSB D15 D14 D13 D12 D11 D10 D9 D8 D7 16-BIT DATA WORD D6 D5 D4 D3 D2 D1 LSB D0
CONTROL REGISTER
The CONTROL register is addressed by setting the control word of the input shift register to 0x55. The data to be written to the CONTROL register is entered in positions D15 to D0 as shown in Table 13. The CONTROL register functions are shown in Table 14.
Table 13. Programming the CONTROL Register
MSB D15 0 D14 0 D13 REXT D12 OUTEN D11 D10 D9 SR CLOCK D8 D7 D6 D5 SR STEP D4 SREN D3 DCEN D2 R2 D1 R1 LSB D0 R0
Table 14. Control Register Functions
Option REXT Description Setting this bit selects the external current setting resistor, Further details in Features section Output enable. This bit must be set to enable the output. See Features Section. Digital Slew Rate Control See Features Section. Digital Slew Rate Control Digital Slew Rate Control enable Daisychain enable Output range select. See Table 15
Table 15. Output Range Options
R2 1 1 1 R1 0 1 1 R0 1 0 1 Output Range Selected 4 to 20 mA Current Range 0 to 20 mA Current Range 0 to 24 mA Current Range
OUTEN SR CLOCK SR STEP SREN DCEN R2,R1,R0
Rev. PrE | Page 21 of 30
AD5410/AD5420
RESET REGISTER
Preliminary Technical Data
The RESET register is addressed by setting the control word of the input shift register to 0x56. The data to be written to the RESET register is entered in positions D15 to D0 as shown in Table 16. The RESET register options are shown in Table 16 and Table 17.
Table 16. Programming the CONTROL 2 Register
MSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB D0 RESET
Table 17. Control 2 register Functions
Option RESET Description Setting this bit performs a reset operation, restoring the AD5410/AD5420 to its initial power on state
STATUS REGISTER
The STATUS register is a read only register. The STATUS register functionality is shown in Table 18 and Table 19.
Table 18. Decoding the STATUS Register
MSB D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 IOUT FAULT D1 SLEW ACTIVE LSB D0 OVER TEMP
Table 19. STATUS Register Functions
Option IOUT FAULT SLEW ACTIVE OVER TEMP Description This bit will be set if a fault is detected on the IOUT pin. This bit will be set while the output value is slewing (slew rate control enabled) This bit will be set if the AD5410/AD5420 core temperature exceeds approx. 150C.
Rev. PrE | Page 22 of 30
Preliminary Technical Data FEATURES
FAULT ALERT
The AD5410/AD5420 is equipped with a FAULT pin, this is an open-drain output allowing several AD5410/AD5420 devices to be connected together to one pull-up resistor for global fault detection. The FAULT pin is forced active by any one of the following fault scenarios; 1) The Voltage at IOUT attempts to rise above the compliance range, due to an open-loop circuit or insufficient power supply voltage. The IOUT current is controlled by a PMOS transistor and internal amplifier as shown in Figure 34. The internal circuitry that develops the fault output avoids using a comparator with "window limits" since this would require an actual output error before the FAULT output becomes active. Instead, the signal is generated when the internal amplifier in the output stage has less than approxiamately one volt of remaining drive capability (when the gate of the output PMOS transistor nearly reaches ground). Thus the FAULT output activates slightly before the compliance limit is reached. Since the comparison is made within the feedback loop of the output amplifier, the output accuracy is maintained by its open-loop gain and an output error does not occur before the FAULT output becomes active. If the core temperature of the AD5410/AD5420 exceeds approx. 150C.
AD5410/AD5420
EXTERNAL CURRENT SETTING RESISTOR
Referring to Figure 34, R1 is an internal sense resistor as part of the voltage to current conversion circuitry. The stability of the output current over temperature is dependent on the stability of the value of R1. As a method of improving the stability of the output current over temperature an external precision 15k low drift resistor can be connected to the RSET pin of the AD5410/AD5420 to be used instead of the internal resistor R1. The external resistor is selected via the CONTROL 1 register. See Table 13.
DIGITAL POWER SUPPLY
By default, the DVCC pin accepts a power supply of 2.7V to 5.5V, alternatively, via the DVCC SELECT pin an internal 4.5V power supply may be output on the DVCC pin for use as a digital power supply for other devices in the system or as a termination for pull-up resistors. This facility offers the advantage of not having to bring a digital supply across an isolation barrier. The internal power supply is enabled by leaving the DVCC SELECT pin unconnected. To disable the internal supply DVCC SELECT should be tied to 0V. DVCC is capable of supplying up to 5mA of current, for a load regulation graph see Figure TBD.
EXTERNAL BOOST FUNCTION
The addition of an external boost transistor as shown in Figure 36 will reduce the power dissipated in the AD5410/AD5420 by reducing the current flowing in the on-chip output transistor (dividing it by the current gain of the external circuit). A discrete NPN transistor with a breakdown voltage, BVCEO, greater than 60V can be used. The external boost capability has been developed for those users who may wish to use the AD5410/AD5420 at the extremes of the supply voltage, load current and temperature range. The boost transistor can also be used to reduce the amount of temperature induced drift in the part. This will minimise the temperature induced drift of the on-chip voltage reference, which improves drift and linearity.
BOOST MJD31C OR 2N3053
2)
The OPEN CCT and OVER TEMP bits of the STATUS register are used in conjunction with the FAULT pin to inform the user which one of the fault conditions caused the FAULT pin to be asserted. See Table 18 and Table 19.
ASYNCHRONOUS CLEAR (CLEAR)
CLEAR is an active high clear that clears the Current output to the bottom of its programmed range. It is necessary to maintain CLEAR high for a minimum amount of time (see Figure 2) to complete the operation. When the CLEAR signal is returned low, the output remains at the cleared value. The pre-clear value can be restored by pulsing the LATCH signal low without clocking any data. A new value cannot be programmed until the CLEAR pin is returned low.
AD5410/ AD5420
IOUT
INTERNAL REFERENCE
The AD5410/AD5420 contains an integrated +5V voltage reference with initial accuracy of 2mV max and a temperature drift coefficient of 10 ppm max. The reference voltage is buffered and externally available for use elsewhere within the system. See Figure 32 for a load regulation graph of the Integrated reference.
0.022 F
1k
RLOAD
Figure 36. External Boost Configuration
Rev. PrE | Page 23 of 30
AD5410/AD5420
DIGITAL SLEW RATE CONTROL
The Slew Rate Control feature of the AD5410/AD5420 allows the user to control the rate at which the output current changes. With the slew rate control feature disabled the output currrent will change at a rate limited by the output drive circuitry and the attached load. If the user wishes to reduce the slew rate this can be achieved by enabling the slew rate control feature.With the feature enabled via the SREN bit of the CONTROL register, (See Table 13) the output, instead of slewing directly between two values, will step digitally at a rate defined by two parameters accessible via the CONTROL register as shown in Table 13. The parameters are SR CLOCK and SR STEP. SR CLOCK defines the rate at which the digital slew will be updated SR STEP defines by how much the output value will change at each update. Together both parameters define the rate of change of the output current.Table 20 and Table 21 outline the range of values for both the SR CLOCK and SR STEP parameters.
Table 20. Slew Rate Update Clock Options
SR CLOCK 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Update Clock Frequency (Hz)
257732 198413 152439 131579 115741 69444 37594 25773 20161 16026 10288 8278 6897 5525 4237 3300
Preliminary Technical Data
Table 21. Slew Rate Step Size Options
SR STEP 000 001 010 011 100 101 110 111 AD5410 Step Size (LSBs) 1 16 1/4 1/2 1 2 4 8 AD5420 Step Size (LSBs) 1 2 4 8 16 32 64 128
The time it will take for the output current to slew over a given output range can be expressed as follows.
SlewTime =
Where:
OutputChange StepSize x UpdateClockFrequency x LSBSize
Slew Time is expressed in seconds Output Change is expressed in Amps
When the slew rate control feature is enabled, all output changes will change at the programmed slew rate, i.e. if the CLEAR pin is asserted the output will slew to the clear value at the programmed slew rate. The output can be halted at its current value with a write to the CONTROL register. To avoid halting the output slew, the SLEW ACTIVE bit can be read to check that the slew has completed before writing to the AD5410/AD5420 registers. See Table 18. The update clock frequency for any given value will be the same for all output ranges. The step size however will vary across output ranges for a given value of step size as the LSB size will be different for each output range. Table 22 shows the range of programmable slew times for a full-scale change on any of the output ranges. The values were obtained using the Slew Time equation above.
Rev. PrE | Page 24 of 30
Preliminary Technical Data
Table 22. Programmable Slew Time values in seconds for a full scale change on any output range.
1 0.25 0.33 0.43 0.50 0.57 0.9 1.7 2.5 3.3 4.1 6.4 7.9 9.5 12 15 20 2 0.13 0.17 0.21 0.25 0.28 0.47 0.87 1.3 1.6 2.0 3.2 4.0 4.8 5.9 7.7 9.9 4 0.06 0.08 0.11 0.12 0.14 0.24 0.44 0.64 0.81 1.0 1.6 2.0 2.4 3.0 3.9 5.0 8 0.03 0.04 0.05 0.06 0.07 0.12 0.22 0.32 0.41 0.51 0.80 1.0 1.2 1.5 1.9 2.5 Step Size (LSBs) 16 0.016 0.021 0.027 0.031 0.035 0.06 0.11 0.16 0.20 0.26 0.40 0.49 0.59 0.74 0.97 1.24 32 0.008 0.010 0.013 0.016 0.018 0.03 0.05 0.08 0.10 0.13 0.20 0.25 0.30 0.37 0.48 0.62
AD5410/AD5420
257732 198413 152439 131579 115741 69444 37594 25773 20161 16026 10288 8278 6897 5525 4237 3300
64 0.004 0.005 0.007 0.008 0.009 0.015 0.03 0.04 0.05 0.06 0.10 0.12 0.15 0.19 0.24 0.31
128 0.0020 0.0026 0.0034 0.0039 0.0044 0.007 0.014 0.020 0.025 0.03 0.05 0.06 0.07 0.09 0.12 0.16
Update Clock Frequency (Hz)
IOUT FILTERING CAPACITORS (LFCSP PACKAGE)
Two capacitors may be placed between the pins CAP1, CAP2 and AVDD as shown in Figure 37.
AVDD C1 AVDD CAP1 C2
alternative to the Digital Slew Rate Control feature or in addition to it as a means of smoothing out the steps caused by the digital code increments.
C1 C2
CAP1
CAP2
AVDD
R3 R2 BOOST
AD5410/ AD5420
GND
CAP2
DAC 12.5K 40K
IOUT
IOUT
R1
Figure 37. IOUT Filtering Capacitors
These two pins are only available on the LFCSP package.The capacitors form a filter on the current output circuitry as shown in Figure 38, reducing the bandwidth and the rate of change of the output current. These capacitors can be used as an
Figure 38. IOUT Filter Ciruitry
Rev. PrE | Page 25 of 30
AD5410/AD5420 APPLICATIONS INFORMATION
DRIVING INDUCTIVE LOADS
When driving inductive or poorly defined loads connect a 0.01F capacitor between IOUT and GND. This will ensure stability with loads beyond 50mH. There is no maximum capacitance limit. The capacitive component of the load may cause slower settling, The digital Slew Rate Control feature may also prove useful in this situation.
Preliminary Technical Data
ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. The power supply lines of the AD5410/AD5420 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board and should never be run near the reference inputs. A ground line routed between the SDIN and SCLK lines helps reduce crosstalk between them (not required on a multilayer board that has a separate ground plane, but separating the lines helps). It is essential to minimize noise on the REFIN line because it couples through to the DAC output. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feed through the board. A microstrip technique is by far the best, but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground plane, while signal traces are placed on the solder side.
TRANSIENT VOLTAGE PROTECTION
The AD5410/AD5420 contains ESD protection diodes which prevent damage from normal handling. The industrial control environment can, however, subject I/O circuits to much higher transients. In order to protect the AD5410/AD5420 from excessively high voltage transients , external power diodes and a surge current limiting resistor may be required, as shown in Figure 39. The constraint on the resistor value is that during normal operation the output level at IOUT must remain within its voltage compliance limit of AVDD - 2.5V and the two protection diodes and resistor must have appropriate power ratings. Further protection can be provided with Transient Voltage Suppressors or Transorbs, these are available as both unidirectional (protects against positive high voltage transients) and bidirectional (protects against both positive and negative high voltage transients) and are available in a wide range of standoff and breakdown voltage ratings. It is recommended that all field connected nodes are protected.
AVDD
GALVANICALLY ISOLATED INTERFACE
In many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that might occur. The iCoupler(R) family of products from Analog Devices provides voltage isolation in excess of 2.5 kV. The serial loading structure of the AD5410/AD5420 make it ideal for isolated interfaces because the number of interface lines is kept to a minimum. Figure 40 shows a 4-channel isolated interface to the AD5410/AD5420 using an ADuM1400. For further information, visit http://www.analog.com/icouplers.
AVDD AD5410/ AD5420 IOUT RP RLOAD
AGND
Figure 39. Output Transient Voltage Protection
LAYOUT GUIDELINES
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5410/AD5420 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5410/AD5420 is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device. The AD5410/AD5420 should have ample supply bypassing of 10 F in parallel with 0.1 F on each supply located as close to the package as possible, ideally right up against the device. The 10 F capacitors are the tantalum bead type. The 0.1 F capacitor should have low effective series resistance (ESR) and low effective series inductance (ESI) such as the common
Controller Serial Clock Out Serial Data Out SYNC Out Control out
ADuM1400 * VIA VIB VIC VID ENCODE ENCODE ENCODE ENCODE DECODE DECODE DECODE DECODE VOA VOB VOC VOD To SCLK To SDIN To LATCH To CLEAR
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 40. Isolated Interface
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5410/AD5420 is via a serial bus that uses protocol compatible with microcontrollers and DSP processors. The communications channel is a 3-wire (minimum) interface consisting of a clock signal, a data signal,
Rev. PrE | Page 26 of 30
Preliminary Technical Data
and a latch signal. The AD5410/AD5420 require a 24-bit dataword with data valid on the rising edge of SCLK. For all interfaces, the DAC output update is initiated on the rising edge of LATCH. The contents of the registers can be read using the readback function.
AD5410/AD5420
be controlled or AVDD should be reduced. The conditions will depend on the device and package. At maximum ambient temperature of 85C the AD5410/AD5420AREZ (24-lead TSSOP) can dissipate 950mW and the AD5410/AD5420ACPZ (40-lead LFCSP) can dissipate 1.42W. To ensure the junction temperature does not exceed 125C while driving the maximum current of 24mA directly into ground (also adding an on-chip current of 3mA), AVDD should be reduced from the maximum rating to ensure the package is not required to dissipate more power than stated above. See Table 23, Figure 41 and Figure 42.
THERMAL AND SUPPLY CONSIDERATIONS
The AD5410/AD5420 is designed to operate at a maximum junction temperature of 125C. It is important that the device is not operated under conditions that will cause the junction temperature to exceed this value . Excessive junction temperature can occur if the AD5410/AD5420 is operated from the maximum AVDD and driving the maximum current (24mA) directly to ground. In this case the ambient temperature should
2.5
TSSOP LFCSP
65 60 55
2 Power Dissipation (W)
TSSOP LFCSP
Supply Voltage (V)
1.5
50 45 40 35 30
1
0.5
0 40 45 50 55 60 65 70 Ambient Temperature (C) 75 80 85
25 25 35 45 55
Ambient Temperature (C)
65
75
85
Figure 41. Maximum Power Dissipation Vs Ambient Temperature
Figure 42. Maximum Supply Voltage Vs Ambient Temperature
Table 23. Thermal and Supply considerations for each package
TSSOP Maximum allowed power dissipation when operating at an ambient temperature of 85C Maximum allowed ambient temperature when operating from a supply of 40V/60V and driving 24mA directly to ground. Maximum allowed supply voltage when operating at an ambient temperature of 85C and driving 24mA directly to ground. LFCSP
TJ max - TA JA
=
125 - 85 42
= 950 mW
TJ max - TA JA
=
125 - 85 28
= 1.42W
TJ max - PD x JA = 125 - 40 x 0.027 x 42 = 79C
TJ max - TA AI DD x JA 125 - 85 0.027 x 42
(
)
TJ max- PD x JA = 125 - 60 x 0.027 x 28 = 79C
TJ max - TA AI DD x JA 125 - 85 0.027 x 28
(
)
=
= 35V
=
= 53V
Rev. PrE | Page 27 of 30
AD5410/AD5420 OUTLINE DIMENSIONS
7.90 7.80 7.70 5.02 5.00 4.95
Preliminary Technical Data
24
13
4.50 4.40 4.30 6.40 BSC
1 12
EXPOSED PAD (Pins Up)
3.25 3.20 3.15
TOP VIEW 1.20 MAX 1.05 1.00 0.80 0.65 BSC 0.30 0.19
BOTTOM VIEW
8 0 0.20 0.09 0.75 0.60 0.45
COMPLIANT TO JEDEC STANDARDS MO-153-ADT
Figure 43. 24-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP] (RE-24) Dimensions shown in millimeters
6.00 BSC SQ 0.60 MAX
31 30 40 1
0.60 MAX PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
5.75 BCS SQ
0.50 BSC 0.50 0.40 0.30
EXPOSED PAD
(BOT TOM VIEW)
4.25 4.10 SQ 3.95
10 11
21 20
0.25 MIN 4.50 REF
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM
1.00 0.85 0.80
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
Figure 44. 40-Lead Lead Frame Chip Scale Package (CP-40) Dimensions shown in millimeters
ORDERING GUIDE
Model AD5410AREZ AD5410ACPZ AD5420AREZ AD5420ACPZ Resolution 12 Bits 12 Bits 16 Bits 16 Bits AVDD max 40V 60V 40V 60V Temperature Range -40C to 85C -40C to 85C -40C to 85C -40C to 85C Package Description 24 Lead TSSOP_EP 40 Lead LFCSP 24 Lead TSSOP_EP 40 Lead LFCSP Package Option RE-24 CP-40 RE-24 CP-40
Rev. PrE | Page 28 of 30
101306-A
SEATING PLANE
0.30 0.23 0.18
0.20 REF
COPLANARITY 0.08
050806-A
SEATING PLANE 0.10 COPLANARITY
0.15 0.05
Preliminary Technical Data
AD5410/AD5420
Rev. PrE | Page 29 of 30
AD5410/AD5420 NOTES
Preliminary Technical Data
(c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR07027-0-5/08(PrE)
Rev. PrE | Page 30 of 30

▲Up To Search▲

Price & Availability of AD5410ACPZ

	To Download AD5410ACPZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .